As integrated circuitry memory cells become increasingly smaller, it becomes more difficult to realize desired memory cells which have enough cell capacitance to store information for a reasonable amount of time. The industry has approached the challenge of providing cell capacitance from two different directions.
According to a first direction, storage capacitors are fabricated over a semiconductor wafer. Such capacitors, known as container capacitors, are typically formed by etching into an insulating layer which is formed over a wafer outer surface. One disadvantage of this approach is that as the memory cells continue to decrease in size, the capacitors have to become narrower and taller in construction in order to maintain a desirable capacitance. Accordingly, the topology of the wafer becomes worse from the standpoint of its impact on several processing steps such as lithography, etching, and mechanical substrate abrading such as chemical mechanical polishing.
According to a second direction, trenches are etched into a substrate and capacitors are formed within the trenches. Such capacitors are known as trench capacitors. A major disadvantage of this approach is that very deep, high aspect ratio trenches must be etched into the substrate. Additionally, complicated strapping mechanisms must be employed to ground the cell.
This invention grew out of concerns associated with increasing cell capacitance while reducing topography and strapping requirements.